Recently, Intel has
published a page showing the step-by-step process of how a CPU is made. From sand to its final product, there are many complex steps involved. In fact, it’s absolutely amazing that semiconductor products work at all.
At about 25% (by mass), silicon is the second most frequent chemical in the earth’s crust (behind oxygen). Sand has a high percentage of Silicon Dioxide (SiO2), which is the base ingredient for semiconductor manufacturing.
Step 2 – Melted Silicon
Silicon is purified in multiple steps to reach the Electronic Grade Silicon used in semiconductors. It ultimately arrives in mono crystal ingots about 12″ in diameter (300mm today, the older ingots were 8″ or 200mm in diameter and smaller — the first wafers in the 1970s were 2″ in diameter, or 50mm).
The purity at this level of refinement is about one part per billion, meaning only one foreign atom per billion silicon atoms. The ingot weighs about 220lbs, and is a 99.9999% pure vertical column of slick glass-looking material.
Step 3 – Ingot Slicing
The ingot is cut with a very thin saw into individual silicon slices (called wafers), each of which are then polished to a flawless mirror-smooth surface. It is upon this totally smooth wafer surface that the tiny copper wires are deposited in the following several steps.
Step 4 – Photo Resist, Exposure
A photo resist liquid is poured onto the wafer while it spins at high speed (similar to materials used in conventional photography). This spinning deposits a thin and even resist layer across the entire surface.
From there, an ultraviolet laser is shone through masks and a lens (which make a focused image 4x smaller than the mask) causing tiny illuminated UV lines on the surface. Everywhere these lines strike the resist, a chemical reaction takes place making those portions soluble.
Step 5 – Washing, etching
The soluble photo resist material is then completely dissolved by a chemical solvent. From there, an etching chemical is used to partially dissolve (or etch) away a tiny quantity of the polished semiconductor material (the substrate). Finally, the remainder of the photo resist material is removed through a similar washing process, revealing the etched surface of the wafer.
Step 6 – Building up layers
In order to create the tiny copper wires which ultimately convey electricity to/from the chip’s various connectors, additional photo resists are added, exposed and washed. Next, a process called ion implantation is used to dope and protect locations where copper ions are deposited from a copper sulfate solution in a process called electroplating.
At various stages during these processes, additional materials are added, exposed, washed / etched and polished. This process is repeated six times for six-layer processes, which is reportedly what Intel uses for their current 45nm high-k, metal gate processes.
The final product looks like a jungle gym, a a host of tiny copper bars which convey electricity. Some of these are connected, some are exactly a specific distance away from other ones. And all of them are used for one purpose: To convey electrons, wielding their electromagnetic effects in a particular way to conduct what we would call “useful work” (such as adding two numbers together at extremely high rates of speed, the very essence of modern day computing).
This multi-layer process is repeated at every single spot on the surface of the entire wafer where chips can be made. This includes even those areas which are partially off the edge of the wafer. Why waste that space? It’s because the early chip makers learned that if they did not fill in these areas with (obviously) wasted semiconductor material, that the chips nearby also had a higher failure rate.
Step 7 – Testing
Once all of the metal layers are built up, and the circuits (transistors) are all created, it’s time for testing. A device with lots of prongs sits down on top of the chip, attaching microscopic leads to the chip’s surface. Each lead completes an electrical connection within the chip, simulating how it would operate in final form once packaged into end-consumer products.
A series of test signals are sent to the chip with whatever the results are being read. This level of testing includes not only traditional computational abilities, but also internal diagnostics along with voltage readings, cascade sequences (does data flow through as it should), etc. And however the chip responds as a result of this testing, is what’s stored in a database assigned specifically for that die.
This process is repeated for every die on the entire wafer’s surface while all dies are still on the surface.
Step 8 – Slicing
A tiny diamond-tipped saw is used to cut the silicon wafer into its various dies. The database derived in Step 7 is used to determine which chips cut from the wafer are kept, and which are discarded. The ones which produced “the right results” in Step 7′s testing are kept, with the rest being thrown away.
Step 9 – Packaging
At this point, all working dies get put into a physical package. It’s important to note that while they’ve had preliminary tested and were found to operate correctly, this doesn’t mean they’re good CPUs.
The physical packaging process involves placing the silicon die onto a green substrate material, to which tiny gold leads are connected to the chip’s pins or ball grid array, which show through the bottom side of the package. On the top of that, a heat spreader is introduced. This appears as the metal package on top of a chip. When finished, the CPU looks like a traditional package end-consumers buy.
Note: The metal heat spreader is a crucial component on modern high-speed semiconductors. In the past, a ceramic top was used with no active cooling. It wasn’t until the 80386 and later time frame, along with some extreme high-speed 8086 and 80286 (100MHz models), that active cooling was required. Prior to that, the chips had so few transistors (the original 8086 had 29K, today’s CPUs have 100s of millions) that they didn’t generate enough heat to require active cooling. To separate themselves, these later ceramic chips were stamped with the warning: “Heatsink required”.
Modern CPUs generate enough heat to melt themselves in a few seconds. Only by having the heat spreader connected to a large heat sink (and fan) can they operate long-term as they do.
Step 10 – Binning
At this point the package looks like you or I will buy it. Still, there is one more step involved. This final step is called binning.
In this process, the actual characteristics of this particular CPU is measured. Items such as voltage, frequency, performance, heat generation and other internal operational characteristics of its cache, for example, are all measured.
The best chips are generally binned as higher-end parts, being sold as not only the fastest parts with their full caches enabled, but also the low-voltage and ultra low-voltage models. Note: Based on market demand, these highest-end chips can also be sold as lesser chip parts.
Chips which do not perform as well as the best chips are often sold for lower clock speed models, or as a triple- or dual-core (Phenom X3, Phenom X2) instead of their native quad-core. Others may have half their cache disabled (Celeron), etc.
Performance and Operational Yields
The process of binning ultimately determines the final yield at given speeds, voltages and thermal characteristics. For example, on a standard wafer only 5% of the chips produced might operate at the highest-end clock rate of 3.2GHz. However, 50% may operate at 2.8GHz.
While this performance yield does not relate to operational yield, it is equally as important to manufacturers as they are constantly looking to determine the reasons why one CPU might operate at 2.8GHz without issue, but not faster, while another operates at 3.2GHz. As the cause of this discrepancy is determined, sometimes the chip’s very design can be updated to increase the performance yield (and operational yields).
Additional Info
Break-even operational yields on most semiconductor products comes between 33% and 50%, meaning if at least 1/3rd to 1/2 of the dies on every wafer work, the company makes breaks even. Anything beyond that is profit. Note: This isn’t always the case, but is a good guideline.
A mature process doesn’t always relate to the time involved in manufacturing dies, but rather is one generally considered to be in excess of an 80% operational yield, with a relatively high performance yield.
Intel is rumored to have around 95% operational yields on mature processes, which on 45nm processes on 300mm wafers means a tremendous advantage in production with their many fabs. A 95% operational yield means if 500 dies were possible from a single wafer, 475 of them would be usable, and only 25 would be thrown out. The more dies per wafer, the more money the company makes.
CPUs go through several iterations, called steps, during their design. The first silicon is called A-0 silicon, then A-1, A-2 and so on. Once a major redesign is implemented, such as adding a larger cache, a new math ability or some other major thing, they move to B-0, then B-1, B-2 and so on. Sequential letters are not required, and many of Intel’s current CPUs are at
step R-0.
During the Pentium Pro through Pentium III days, each revision to that design was just that: A Revision. The difference between Pentium II and Pentium III, for example, was the inclusion of SIMD instructions and its original SSE ISA extension. However, this design received continued tweaking, which allowed it to move from its original 450MHz clock speed up to its final 1.4GHz in various forms, the last of which, Tualatin, operated faster than early Pentium 4s, due to its shorter pipeline.
Conclusion / Opinion
I hope you’ve found this article informative. It is truly amazing that any CPU operates, let alone as many as they manufacture and as fast as they do. And what’s coming is even more impressive.
The difference between x86, ARM, DRAM, SoCs, ASICs and other semiconductor variations, for example, often times is found only in the wiring. The exact same manufacturing steps and processes are used to produce those various products (with sometimes a different number of layers, sometimes different laser light, sometimes different chemicals, etc.). But generally speaking, it’s all “in the programming”, so to speak — in that copper-wire-based zoo of lines which, based on their arrangement, wield the mystic forces of electromagnetism into usable human work.
Quite a thing, wouldn’t you say?
