Passive and Semi-Passive Wireless Temperature and Humidity Sensors Based on EPC Generation-2 UHF Protocol

https://www.researchgate.net/publication/273394748_Passive_and_Semi-Passive_Wireless_Temperature_and_Humidity_Sensors_Based_on_EPC_Generation-2_UHF_Protocol

Passive and Semi-Passive Wireless Temperature and Humidity Sensors Based on EPC Generation-2 UHF Protocol

ABSTRACT

This paper proposes passive and semi-passive wireless temperature and humidity sensors based on electronic product code (EPC) global Class-1 Generation-2 UHF communication protocol. The wireless sensors consist of a sensor key chip and off-chip temperature and humidity sensors. The sensor key chip integrates RF/analog front-end circuit, digital baseband processor, nonvolatile memory, on-chip temperature sensor, and sensor interface. The sensor interface connects the off-chip sensors and the sensor key chip. The sensor key chip with the on-chip temperature sensor can operate without battery power (passive mode), and also can co-operate with the off-chip temperature and humidity sensors powered by battery (semi-passive mode). The RF/analog front-end circuit provides the dc power to the sensor key chip and communicates with the interrogator passively. Advanced low-power techniques are adopted to reduce the power consumption of the sensor key chip. The sensor key chip is fabricated in 0.18-μm CMOS process. In passive mode, the maximum wireless sensitivity of on-chip sensor is -15.1/-11.2 dBm for reading and sensing operation, respectively, and the temperature sensing error is -1 °C/0.8 °C over operating range from -20 °C to 50 °C. It achieves a reading/sensing distance of over 9.5/6 m with 4-W effective isotropic radiated power (EIRP) by the commercial interrogator. In semi-passive mode, the temperature and humidity sensing distance of off-chip sensors is 2.7 m.

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Passive and Semi-Passive Wireless Temperature

and Humidity Sensors Based on EPC Generation-

2 UHF Protocol

ARTICLE in IEEE SENSORS JOURNAL · APRIL 2015

Impact Factor: 1.76 · DOI: 10.1109/JSEN.2014.2375180

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Chinese Academy of Sciences

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Nan-Jian Wu

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IEEE SENSORS JOURNAL, VOL. 15, NO. 4, APRIL 2015 2403

Passive and Semi-Passive Wireless Temperature

and Humidity Sensors Based on EPC

Generation-2 UHF Protocol

Shuang-Ming Yu, Peng Feng, and Nan-Jian Wu, Member, IEEE

Abstract—This paper proposes passive and semi-passive

wireless temperature and humidity sensors based on electronic

product code (EPC) global Class-1 Generation-2 UHF communication

protocol. The wireless sensors consist of a sensor

key chip and off-chip temperature and humidity sensors. The

sensor key chip integrates RF/analog front-end circuit, digital

baseband processor, nonvolatile memory, on-chip temperature

sensor, and sensor interface. The sensor interface connects

the off-chip sensors and the sensor key chip. The sensor key

chip with the on-chip temperature sensor can operate without

battery power (passive mode), and also can co-operate with the

off-chip temperature and humidity sensors powered by battery

(semi-passive mode). The RF/analog front-end circuit provides

the dc power to the sensor key chip and communicates with

the interrogator passively. Advanced low-power techniques are

adopted to reduce the power consumption of the sensor key

chip. The sensor key chip is fabricated in 0.18-μm CMOS

process. In passive mode, the maximum wireless sensitivity of

on-chip sensor is −15.1/−11.2 dBm for reading and sensing

operation, respectively, and the temperature sensing error is

−1 °C/0.8 °C over operating range from −20 °C to 50 °C.

It achieves a reading/sensing distance of over 9.5/6 m with

4-W effective isotropic radiated power (EIRP) by the commercial

interrogator. In semi-passive mode, the temperature and humidity

sensing distance of off-chip sensors is 2.7 m.

Index Terms—Wireless sensors, temperature sensors, humidity

sensors, sensor interface, baseband processor, EPC global Class-1

Generation-2 protocol, passive tags, low power design.

I. INTRODUCTION

NOWADAYS, various kinds of wireless sensors have been

widely used in many applications because they can be

Manuscript received October 20, 2014; revised November 17, 2014;

accepted November 19, 2014. Date of publication November 26, 2014; date

of current version February 10, 2015. This work was supported in part by the

National Key Technology Research and Development Program through the

Ministry of Science and Technology of China under Grant 2012BAH20B02,

in part by the National High Technology Research and Development Program

of China under Grant 2012AA012301, in part by the National Science and

Technology Major Projects through the Ministry of Science and Technology

of China under Grant 2012ZX03004007-002, in part by the National Natural

Science Foundation of China under Grant 61306027, and in part by the

Academy-Locality Cooperation Program, Chinese Academy of Sciences,

Beijing, China. The associate editor coordinating the review of this paper

and approving it for publication was Prof. Sang-Seok Lee.

The authors are with the State Key Laboratory for Superlattices and

Microstructures, Institute of Semiconductors, Chinese Academy of Sciences,

Beijing 100089, China (e-mail: yushuangming@semi.ac.cn; fengpeng06@

semi.ac.cn; nanjian@red.semi.ac.cn).

Color versions of one or more of the figures in this paper are available

online at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/JSEN.2014.2375180

easily arranged in the fields [1]–[5]. For example, wireless sensors

are increasingly applied to extreme condition detecting,

high-risk environment surveillance, emergency rescue, frozen

food transportation, and tracking humidity and pressure of

scientific equipment [6].

The wireless sensors usually include wireless communication

technologies, such as ZigBee, Bluetooth and wireless

local area networks, to receive commands and transmit

data [7]–[14]. A ZigBee-based intelligent self-adjusting

sensor for home energy management service is implemented

by using ZigBee wireless technology for networking and

communication [7]. Another ZigBee-based non-invasive wearable

monitoring device for physiological parameters, such as

temperature and heart rate of a human subject, has been

developed and reported [8]. A Bluetooth module is selected

to act as a virtual serial data port for digital temperature sensors

in rotor temperature measurement [12]. However, those

wireless technologies are usually used to form sensor networks

for environment monitoring and diagnostics of electric

drives [13]. They have drawbacks of high power consumption,

large device size, high complexity of operation, and low

flexibility.

The passive RFID tag technology exhibits benefits of very

simple structure, low cost and low power. The tags are able

to passively communicate with the interrogator in a zeropowered

backscatter mechanism. Therefore, wireless sensors

based on the passive tag technology have raised increasing

interest among academic and industrial research [15]–[19].

An energy-efficient wireless sensing within a passive multistandard

RFID transponder is enabled by using a successive

approximation analog-digital converter [15]. Another wireless

temperature sensor tag chip is presented with the extra

circuit modules, such as external temperature sensor and

ADC [16]. A passive RFID tag embedded temperature sensor

with time-domain readout scheme for a −30 °C to 60 °C

sensing range was reported [17]. TELID412 RFID sensor by

MicroSENSYS [18] and Fenix RFID Tag by Farsens [19] are

designed as passive RFID sensor devices without sensor interface

for off-chip sensor devices. However, in many applications,

some non-CMOS-compatible sensors, such as humidity

and pressure sensors are also required to be integrated in the

system.

Recently, wireless sensors which include a RFID tag

chip with a sensor interface and off-chip sensors has been

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2404 IEEE SENSORS JOURNAL, VOL. 15, NO. 4, APRIL 2015

proposed [20]–[26]. An ultra-low-power four-channel sensor

interface for wireless semi-active RFID transponders based

on a switched-capacitor sigma-delta modulator was described

in [20]. However the analog signal interface is not compatible

with most general off-chip sensors with standard digital

signal interface. RFID sensor prototypes fabricated on a

printed circuit board using discrete components were designed

for full-passive, semi-passive and passive/semi-passive compatible

operation mode [21]–[26]. A solution including a

compact low power microcontroller and a RFID core extended

by a memory unit as data interface was presented in [21].

PE3001 UHF Tag IC by Productivity Engineering (PE) GmbH

was designed with a Serial Peripheral Interface (SPI) which

costs higher pin count than I2C and limits the number of

accessible off-chip sensors [26]. In [23]–[25], the sensors need

external MCU component and extra antenna with off-chip

RF-dc circuit to harvest the RF energy and supply the MCU

and off-chip sensors in passive operation mode. This will

greatly increase the cost and size of the sensor tag.

Comparing with the wireless sensors, where a microcontroller

and an off-the-shelf RFID chip are externally connected,

an ASIC single-chip solution and easier data exchange strategy

between the RFID chip and the microcontroller is more

compact and has a lower power consumption. Therefore, it is

very important to develop a sensor single key chip with wireless

low power communication circuits, on-chip low power

sensor circuits and sensor interface for operating the off-chip

sensors.

This paper proposes passive and semi-passive wireless temperature

and humidity sensors based on EPC global Class-1

Generation-2 (EPC Generation-2) UHF communication

protocol. The wireless sensors consist of a sensor key chip

and off-chip temperature and humidity sensors. The sensor

key chip integrates an on-chip temperature sensor, a sensor

interface and a digital baseband processor. The sensor interface

uses I2C serial bus to connect the off-chip sensors and the

sensor key chip. Some advanced low power techniques are

adopted to effectively reduce the power consumption of the

key chip and to increase the sensing distance. Comparing with

the above-mentioned related works, the proposed wireless sensors

have the following features. First, the sensor key chip with

the on-chip temperature sensor can operate without battery

power (passive mode) and also co-operate with the off-chip

sensors which are powered by a battery (semi-passive mode),

which can be operated by a commercial interrogator. Second,

the sensor key chip implements single-chip solution instead

of using discrete MCU to reduce the power consumption and

cost. Third, the integrated I2C sensor interface can connect

the off-chip sensors and the sensor key chip directly. Fourth,

the sensors are equipped with only one UHF antenna which is

designed and patterned directly on FR4 substrate to perform

both energy-harvesting and communication. This will reduce

the size and cost of the wireless sensors.

The paper is organized as follows. Firstly, the wireless

sensor architecture is presented in Section II. Next, the critical

circuit blocks are designed in Section III. The measurement

results are shown in Section IV. Finally, conclusions are drawn

in Section V.

Fig. 1. Architecture of the wireless sensors.

II. WIRELESS SENSOR ARCHITECTURE

Fig. 1 shows the architecture of the wireless sensors. The

wireless sensors consist of a sensor key chip and off-chip

temperature and humidity sensors. The sensor key chip integrates

RF/analog frontend circuit, digital baseband processor,

non-volatile memory (NVM), on-chip temperature sensor,

and off-chip sensor interface. The communication between

the wireless sensors and the interrogator is based on the

EPC Generation-2 UHF protocol. The wireless sensors can

operate in two modes: passive mode and semi-passive mode.

In passive mode, the wireless sensors can measure temperature

by the on-chip sensor passively. In semi-passive mode, the

wireless sensors can semi-passively measure temperature and

humidity by the off-chip sensors, which are powered by a

battery. The performance of the off-chip temperature sensor is

better than on-chip temperature sensor.

The proposed wireless sensors have several advanced merits.

The interrogator can identify the wireless sensors when there

are a mass of wireless sensors in the application fields.

Secondly the wireless sensors can also execute temperature

sensing operation in passive mode under some battery-less

conditions. Furthermore, when the humidity or high-accuracy

temperature measurements are required, the sensor key chip

can activate the off-chip sensors and perform the measurements

in the semi-passive mode. Therefore, the wireless sensors

can adapt to the various application scenarios flexibly and

improve the battery lifetime.

The communication process between the interrogator and

wireless sensors is described as follows. The interrogator sends

energy and information to the sensor key chip by a modulated

UHF RF carrier. The sensor key chip harvests electrical energy

from the RF carrier, and activates itself. Then the sensor key

chip receives the commands and data from the interrogator

and sends information back by a backscattering scheme. The

communication link between the interrogator and sensor key

chip is half-duplex.

The RF/analog frontend circuit converts the energy of

RF signal into DC power to energize the sensor key chip, and

demodulates (modulates) the received (transmitted) signal. The

digital baseband processor decodes the demodulated signal

and generates the encoded data for modulation. Besides,

the baseband processor executes the received commands and

controls the on-chip and off-chip sensors. The sensor interface,

compatible with the I2C serial bus standard, supports the

communication between the sensor key chip and off-chip

YU et al.: PASSIVE AND SEMI-PASSIVE WIRELESS TEMPERATURE AND HUMIDITY SENSORS 2405

Fig. 2. Block diagram of the digital baseband processor.

sensors. The CMOS-compatible NVM is designed to store the

information such as EPC code, security information or sensing

data after power off.

III. DESIGN AND IMPLEMENTATION OF CIRCUIT BLOCKS

A. Low-Power Digital Baseband Processor

Fig. 2 shows the structure of the proposed digital baseband

processor which is fully compatible with EPC Generation-2

UHF protocol. The system consists of power management

(PM) module, PIE decoder, encoder, command decoder,

state controller, NVM controller, sensor controller, off-chip

sensor interface, cyclic redundancy check (CRC) check

module and slot counter.

In each communication round, the baseband processor

receives the encoded commands and data from the RF/analog

frontend circuit at a rate of 26.7kbps to 128kbps. Then, the

PIE decoder decodes the data symbol and starts the data

processing. The CRC check module calculates the CRC-16

over the received commands or transmitted data to detect error

or protect the certain information. If the CRC check result is

error, all data are discarded and frame is terminated.

The command decoder analyzes and identifies all commands

received from the interrogator. According to the decoded

commands, the state controller performs the corresponding

operations with the input data, such as enabling or disabling

the NVM controller, sensor controller and off-chip sensor

interface respectively.

These commands are responsible for reading data from or

writing data to the NVM, activating the on-chip temperature

sensor, and controlling the off-chip temperature and humidity

sensors through the sensor interface module. Finally the

encoder collects the output frames from the State Controller,

CRC code from CRC check module, and random number

generated in slot counter. The slot counter is designed

based on the Slotted ALOHA algorithm as anti-collision

mechanism [34]. Then, the encoder encodes the output data

according to FM0/Miller encoding method, and sends them

to the modulator for backscattering. The PM module adaptively

and dynamically controls the operations of the circuit

modules of baseband processor to effectively reduce its power

consumption.

We design a set of internal customized commands to

operate the on-chip temperature sensor and off-chip sensors.

Fig. 3. Functional illustration of Power Management Module.

The baseband processor firstly sends the certain command

to start up the on-chip temperature sensor. After finishing

the measurement operation, the baseband processor receives

the sensing result data and saves them into the NVM. The

customized commands also can start up the off-chip sensors,

receive the sensing result data and save them into the NVM

through the I2C interface. The interrogator can read out

the sensing result data in the NVM and finish the sensing

operation.

The designed baseband processor has some advanced

merits. Firstly, it can implement the internal customized

commands and manage the on(off)-chip sensors. Secondly,

it integrates the general I2C serial bus, which can connect any

sensors with I2C serial bus. Thirdly, it is compatible with EPC

Generation-2 protocol. Finally, the wireless sensors operate

in the half-duplex fashion so that a novel PM method can

be designed to activate/shut down the certain circuit modules

adaptively and to reduce the instantaneous power consumption

of the baseband processor.

Because the sensor key chip integrates the on-chip sensor

and I2C serial bus, the power consumption of the chip will

be increased. To improve the operating distance, the power

consumption of the sensor key chip must be minimized. Fig. 3

illustrates the function of the power management module,

which reduce the baseband power consumption.

The operation of the baseband processor is divided into

three kinds of states: RECEIVE state, PROCESS state and

TRANSMIT state. When the baseband processor operates in

RECEIVE state, only PIE decoder and CRC check modules

are activated. After receiving the whole message, processor

turns in to PROCESS state. PM module disables the PIE

decoder and CRC check module, and enables command

decoder and state controller. Then according to the received

commands, state controller performs the corresponding operations,

and prepares the output data. Finally, in TRANSMIT

state, encoder and slot counter module are activated to encode

the message and send the data to the modulator. Thus, the

PM module enables the operating modules and disables the

idle modules dynamically to reduce the power consumption

of the baseband processor.

2406 IEEE SENSORS JOURNAL, VOL. 15, NO. 4, APRIL 2015

Fig. 4. Clock gating and operand isolation techniques.

Fig. 5. Block diagram of the on-chip temperature sensor.

Besides of PM method, other low-power circuit design

techniques are also adopted to reduce the power consumption

of baseband processor. As shown in Fig. 4, clock gating

and operand isolation are used to reduce power consumption

of the modules. These power optimization techniques are

adopted at RTL and logic synthesis level. Clock gating reduces

the switching activity of the sequential cells by turning off

the clock signal. Furthermore, operand isolation is applied

to arithmetic modules to reduce the internal and dynamic

power consumption of the combinational cells. The power

consumption of these cells is reduced by eliminating unwanted

transitions of their inputs when their outputs do not affect any

other cells.

Supply voltage reduction is also an effective method to

reduce the dynamic power consumption. In order to minimize

the power consumption, the processor circuit is designed

to operate at 0.8V. On the other hand, the operating clock

frequency is minimized to further reduce the dynamic power.

The clock frequency is optimized by considering the trade-off

between the sensor performance and the power consumption.

B. Low-Power On-Chip Temperature Sensor and

I2C Serial Bus Interface for Off-Chip Sensors

The low power on-chip temperature sensor is powered by

the energy provided by RF rectifier. The block diagram of

the on-chip temperature sensor is shown in Fig. 5. It consists

of a bipolar sensing core, a low power 2nd-order sigma delta

( ) ADC, a dynamic element match (DEM) control module

and a bias circuit. The ADC includes a modulator,

a decimation filter and a clock generator. The bipolar sensing

core which is biased by a p: 1 ratio currents, produces two

voltage signals VBE1 and VBE2, which are complementary to

absolute temperature (CTAT), and can be expressed as follows:

VBEn = (

kT

q

) · ln(

IC

IS

), n = 1,2 (1)

where k is the Boltzmann constant, q is the electron charge,

T is the temperature in Kelvin, IC is the collector current

and IS is the PNP’s saturation current. The voltage difference

VBE = VBE1 − VBE2 is proportional to absolute temperature

(PTAT), which can be expressed as:

VBE = kT

q

· ln(p) (2)

The relationship among the absolute temperature T ,

VBE2 and VBE can be expressed as [35]:

T = A

α

α + X

(3)

where A is a constant, X = VBE2/ VBE and α is the gain

factor which is chosen to make a band-gap reference voltage

VREF = VBE2 + α VBE. For the temperature range from

−20 °C to 50 °C, in consideration of process corners and

design margins, X will not exceed the range from 5 VBE

to 24 VBE. Then the charge balance scheme can be used to

digitize X in the ADC, and α can be simply trimmed in

the digital backend. In the actual implementation, a 2nd-order

ADC is designed to realize noise shaping and improve

the resolution and conversion speed, and reduce the power

consumption. The modulator implemented with differential

switched-capacitor circuits, adopts DEM method to reduce

the mismatch effect of current sources in the bipolar core

and sampling capacitors in the modulator. As a result of the

2nd-order noise shaping, 13 bits temperature data can be

obtained with only 128 bit streams. The measured temperature

data are stored in the NVM, which can be read out through

commercial interrogator.

The off-chip sensor interface is integrated in this wireless

sensor key chip to manage off-chip temperature and humidity

sensors. It is compatible with I2C serial bus interface standard.

The off-chip sensors and sensor key chip are connected with

two bus lines: a serial data line and a serial clock line.

The EPC operation commands control the sensing commands

and data transmissions through the sensor interface. The

off-chip sensors are recognized as slave (master) devices when

receiving (transmitting) the operation commands (the sensing

data) from (to) the sensor key chip. The interrogator first starts

up the off-chip sensors by a measurement command. After

finishing the sensing operation, the off-chip sensors send back

the sensing result digital data to the sensor key chip. Then,

the result data is stored in NVM. Finally the interrogator can

read out the result data in NVM by an EPC read operation

command and shows the measured temperature and humidity.

C. CMOS UHF Rectifier

The rectifier converts input electromagnetic waves into

DC power for the wireless sensor key chip. The UHF rectifier

in this paper is compatible with a standard CMOS process.

YU et al.: PASSIVE AND SEMI-PASSIVE WIRELESS TEMPERATURE AND HUMIDITY SENSORS 2407

Fig. 6. Circuit architecture of the CMOS rectifier.

Fig. 7. Voltage control methods of the rectifier.

As shown in Fig. 6, the CMOS UHF rectifier is based on a

modified charge pump structure. It consists of six cascaded

rectifier cells and an oscillator. A switched capacitor circuit

technique is used to provide active bias to solve the

threshold voltage problem in MOS diodes. The MOS diodes

(NM1 and PM1) are biased by two circuits (Bias1 and Bias2)

respectively to make them work in sub-threshold region. As a

result, the voltage loss during charge transferring caused by

the threshold voltage of the switch transistors is reduced. This

technique improves the voltage gain of the rectifier cell and

the power efficiency of the rectifier.

Because the incoming electromagnetic wave intensity into

the wireless sensors varies over a 30 dB range, to provide a

stable DC voltage and power, some voltage control methods

must be designed. Fig. 7 shows the schematic diagram of the

voltage control circuits, which include regulator, limiter and

protector. For low level of electromagnetic wave intensity, the

voltage is stabilized by the regulator only. For middle level

of electromagnetic wave intensity, the voltage is stabilized by

the regulator and limiter. The limiter can clamp the voltage

below a certain value. For high level of electromagnetic wave

intensity, the voltage is stabilized by the regulator, limiter and

protector using feedback mechanism. The protector consists

of voltage comparator and a switch connecting to the input

ports of rectifier. The comparator is used to compare output

voltage of rectifier and reference voltage, and the comparison

result controls the switch to change the input impedance of

rectifier. As a result, the input signal intensity can be reduced

and the sensor key chip can be protected.

D. Low Power Single-Poly NVM

NVM embedded in the sensor key chip is used to store

information such as EPC code, security codes and sensing data

Fig. 8. (a) Block diagram of the non-volatile memory. (b) Schematic of the

memory bit cell.

Fig. 9. Microphotograph of the sensor key chip.

after power off [36], [37]. The architecture of the proposed

NVM is shown in Fig. 8(a). It consists of a non-volatile cell

array, a volatile register array, a bit line controller, a column

decoder, a sense amplifier column, a charge pump and a

control logic module. The non-volatile cell array and register

array have the equal numbers of corresponding bits. The data

in the non-volatile array can be first loaded into the register

array for the subsequently read operation with a faster speed

and less power. The charge pump generates a high voltage

and a medium voltage for programming. The column decoder

selects the active column. The sense amplifier column detects

the output data of active-column cells during read operation.

Fig. 8(b) shows the schematic of the memory bit cell.

To minimize the process cost and power consumption, the

NVM is realized with single-poly differential floating gate cell

compatible with standard CMOS process and bi-directional

FN-tunneling to achieve reliable low power programming. The

memory bit cell consists of FN tunneling junctions M1-M4

and coupling capacitors C1 and C2. The electrons can tunnel

through M1 and M2 (M3 and M4) to inject into (depart from)

the floating gates.

IV. MEASUREMENT RESULTS

The sensor key chip has been fabricated in 0.18μm

standard CMOS process with the chip area of 1.44 mm2.

Fig. 9 shows the microphotograph of the sensor key chip.

2408 IEEE SENSORS JOURNAL, VOL. 15, NO. 4, APRIL 2015

Fig. 10. The test platform for the wireless sensors.

Fig. 11. Measurement communication signal waves between wireless sensors

and interrogator.

Fig. 12. Measured backscattered data of FM0-encoded symbols.

Fig. 13. Power consumption for optimization techniques.

Prototype passive and semi-passive wireless temperature and

humidity sensors based on the sensor key chip have been

fabricated on FR4 substrate. As shown in Fig. 10, the wireless

sensors include the sensor key chip, off-chip temperature and

humidity sensors, dipole copper antenna and lithium battery.

Fig. 10 shows the test platform of the wireless sensors.

The commercial interrogator is used to send energy and a

set of commands and data through the antenna. We use a

RFID protocol analyzer to monitor the communication information

between wireless sensors and interrogator. Fig. 11

shows measurement communication signals between wireless

sensors and interrogator. The interrogator uses Select Command

to selects a particular sensor population, and uses Query

command to start the communication process. The selected

sensor will backscatter a 16 bits random number (RN16)

to the interrogator. Then the interrogator will send ACK

command which echoes the RN16 to acknowledge the sensor.

Finally, the sensor will backscatter the data. Fig. 12 shows

the measured backscattered data of FM0-encoded symbols.

Fig. 14. Measurement result of operating off-chip sensors with I2C serial

bus interface.

Fig. 15. Measured temperature error of the on-chip temperature sensor.

The wireless sensors have been further measured according

to EPC Generation-2 UHF protocol. The results show that

the wireless sensors are compatible with the communication

protocol and it can correctly execute reading, writing and

sensing operation.

Fig. 13 shows a comparison of the measured power

consumption for two different baseband processor designs.

The first version of the design without power optimization

techniques consumes 18.5μW at minimum operating voltage

of 0.9V. By using power optimization techniques described

above, the baseband processor consumes only 7.9μW at

minimum operating voltage of 0.8V. The comparison results

show that a 57% power reduction is achieved by using power

optimization techniques.

Fig. 14 shows the measured communication process of the

I2C serial bus interface between the sensor key chip and

the off-chip temperature and humidity sensors. SCL signal

provides the off-chip sensors a continuous stable clock signal,

and SDA signal is used to transmit data and commands

between the sensor key chip and off-chip sensors. The communication

process is divided into three steps. In the first

step, the off-chip sensors receive the address and commands

from the sensor key chip. Then the off-chip sensors begin

to perform the measurement operation. After finishing the

measurement, they outputs the sensing data back to the sensor

key chip through SDA signal line. Finally, the sensing data

is stored in the NVM which can be read out by commercial

interrogator. The measurement results show that the sensor

interface can make the sensor key chip operate the off-chip

sensors.

The measured performance of the rectifier indicates that it

achieves a power efficiency of about 30% at the load resistor of

20k at input power of −5dBm. The measured results of the

YU et al.: PASSIVE AND SEMI-PASSIVE WIRELESS TEMPERATURE AND HUMIDITY SENSORS 2409

TABLE I

PERFORMANCE SUMMARY AND COMPARISON

NVM show that the write power consumption is only 4.3μW

@1.2V supply voltage, which is acceptable in the wireless

sensors. The NVM also shows good endurance performance

of more than 105 write/erase times, and it is fully compatible

with standard CMOS process.

To test the temperature sensing performance, the wireless

temperature sensor, the interrogator antenna and a reference

temperature sensor are placed inside the temperature chamber

with a temperature constancy of ±0.3 °C. Fig. 15 and Fig. 16

show the typical measurement results of the on-chip passive

temperature sensor and the off-chip semi-passive temperature

sensor. The inaccuracy of the on-chip temperature sensor is

−1.0 °C/0.8 °C over operating range from −20 °C to 50 °C

with a resolution of 0.02 °C. The commercial off-chip temperature

sensor also shows good performance, and can achieve a

resolution of 0.04 °C over a range of −40 °C to 125 °C.

2410 IEEE SENSORS JOURNAL, VOL. 15, NO. 4, APRIL 2015

Fig. 16. Measured temperature error of the off-chip temperature sensor.

Fig. 17. Measured humidity error of the off-chip humidity sensor.

To test the humidity sensing performance, the wireless

sensors, the interrogator antenna and a reference humidity

sensor are placed inside a chamber in which the humidity

is adjustable. The commercial off-chip humidity sensor is

energized by a 3V lithium battery. Fig. 17 shows the typical

measurement results of the off-chip humidity sensor. The

off-chip humidity sensor can monitor the humidity with a

resolution of 0.4% over a range of 20% to 98%. Although

the sensing error is limited by the reference sensor and other

non-ideal effects, the wireless sensors show good performance.

Table I summarizes and compares the performances of the

wireless sensors with those of other works. The wireless sensors

successfully measured data using commercial interrogator

with 4W EIRP. It achieved a reading/sensing distance of over

9.5/6.0 m with on-chip sensor, and 2.7 m with off-chip sensors.

The maximum wireless sensitivity is −15.1dBm for reading

operation, −11.2dBm for on-chip passive temperature sensing

operation and −4.2dBm for off-chip semi-passive temperature

and humidity sensing operation, respectively.

Compared with the sensors in [30]–[32], our proposed

wireless sensors integrate the sensor interface for operating

off-chip sensors to expand their application area. Our wireless

sensors also have longer operating distance because of the

ultra-low power NVM, on-chip temperature sensor, baseband

circuit and high efficiency RF rectifier. Compared with the

sensors in [24], our wireless sensors can perform temperature

sensing operation in passive mode without battery power.

Compared with the sensors in [25], our wireless sensors can

perform sensing operation without MCU. This can reduce

the power consumption and cost. Furthermore, our wireless

sensors are equipped with only one UHF antenna designed

and patterned directly on FR4 substrate to perform both

energy-harvesting and communication. This can reduce the

size and cost of the sensors.

V. CONCLUSION

This paper proposed passive and semi-passive wireless

temperature and humidity sensors based on EPC Generation-2

UHF protocol. A sensor key chip and off-chip temperature

and humidity sensors were integrated in the wireless sensors.

The sensor interface in sensor key chip was designed for

connecting the off-chip sensors. The wireless sensors can

be operated in two modes: passive mode and semi-passive

mode. Power management method and clock gating method

were adopted to reduce the power consumption. The sensor

key chip was fabricated in 0.18μm CMOS process occupying

an area of 1.44mm2 . The experimental results indicate

that the wireless sensors can measure temperature by the

on-chip temperature sensor passively, and temperature and

humidity by the commercial off-chip sensors semi-passively.

In passive mode, the maximum wireless sensitivity of the sensor

is −15.1/−11.2dBm for reading and sensing operation of

on-chip sensor, respectively. It achieves a reading/sensing

distance of over 9.5/6.0m with 4W EIRP. In semi-passive

mode, the wireless sensitivity is −4.2dBm for sensing operation

of off-chip sensors, and the sensing distance is 2.7 m.

The wireless sensors can be operated by the commercial

interrogator.

ACKNOWLEDGMENT

The authors would like to thank S. Zhang for his help in

testing.

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Shuang-Ming Yu was born in Liaoning,

China, in 1987. He received the B.S. degree in

electronic science and technology from the Beijing

University of Posts and Telecommunications,

Beijing, China, in 2010. He is currently pursuing

the Ph.D. degree at the State Key Laboratory

for Superlattices and Microstructures, Institute of

Semiconductors, Chinese Academy of Sciences,

Beijing. His current research interest includes

ultralow-power circuit design, digital circuits

design, and radio frequency identification tags.

Peng Feng was born in Chongqing, China, in 1983.

He received the B.S. degree in electronics from

Sichuan University, Chengdu, China, in 2006, and

the Ph.D. degree in microelectronics and solidstate

electronics from the Institute of Semiconductors,

Chinese Academy of Sciences, Beijing, China,

where he has been an Assistant Professor with the

Institute of Semiconductors since 2011. His current

research interests include radio frequency energy

harvesting, embedded CMOS nonvolatile memory,

CMOS-embedded sensors, and RFID tags.

Nan-Jian Wu (M’05) was born in Zhejiang, China,

in 1961. He received the B.S. degree in physics from

Heilongjiang University, Harbin, China, in 1982, the

M.S. degree in electronic engineering from Jilin

University, Changchun, China, in 1985, and the

D.Sc. degree in electronic engineering from the

University of Electronic-Communications, Tokyo,

Japan, in 1992. In 1992, he joined the Research

Center for Interface Quantum Electronics and

the Faculty of Engineering, Hokkaido University,

Sapporo, Japan, as a Research Associate. In 1998, he

was an Associate Professor with the Department of Electro-Communications,

University of Electronic Communications, Tokyo. Since 2000, he has been a

Professor with the Institute of Semiconductors, Chinese Academy of Sciences,

Beijing, China. In 2005, he visited the Research Center for Integrated Quantum

Electronics, Hokkaido University, as a Visiting Professor. In 2009, he

became an Honorable Guest Professor at the Research Institute of Electronics,

Shizuoka University, Shizuoka, Japan. His research is in the field of mixedsignal

LSI design and semiconductor quantum devices

CMOS MEMS Loudspeaker and elecronic ear, thymphanic membran

CMOS MEMS Loudspeaker and elecronic ear, thymphanic membran

If a CMOS MEMS Loudspeaker sending Sound in Newton/mm(F/mm) to the thymphanic membrane(who hear the sound) and do not rely care the distance, passing through material and longer(mm), as more force(N) as more distance from thymphanic membrane, i just think a electronic ear or a human ear could maeby hear it close. A CMOS MEMS Loudspeaker do the same work, and dont care about circumstances.

Richard Svanberg

SoC Issues for RF Smart Dust

http://www.cs.berkeley.edu/~culler/AIIT/papers/radio/Cook%20IEEE%20Proc%202006.pdf

SoC Issues for RF Smart Dust

Wireless sensor nodes, each a self-powered system performing sensing, communication, and computation, form reliable mesh networks coordinating efforts to add intelligence to the environment.

By Ben W. Cook, Student Member IEEE, Steven Lanzisera, Student Member IEEE, and Kristofer S. J. Pister

ABSTRACT | Wireless sensor nodes are autonomous devices incorporating sensing, power, computation, and communication into one system. Applications for large scale networks of these nodes are presented in the context of their impact on the hardware design. The demand for low unit cost and multiyear lifetimes, combined with progress in CMOS and MEMS processing, are driving development of SoC solutions for sensor nodes at the cubic centimeter scale with a minimum number of offchip components. Here, the feasibility of a complete, cubic millimeter scale, single-chip sensor node is explored by examining practical limits on process integration and energetic cost of short-range RF communication. Autonomous cubic millimeter nodes appear within reach, but process complexity and substantial sacrifices in performance involved with a true single-chip solution establish a tradeoff between integration and assembly.

KEYWORDS | Low-power circuits; low-power RF; Smart Dust; wireless mesh networks; wireless sensor networks; wireless sensors I.

INTRODUCTION AND HISTORY The term BSmart Dust[ has come to be used to describe a wide range of wireless sensor network hardware at a small scale down to a handful of cubic millimeters [1]. Each wireless sensor node, or Bmote,[ contains one or more sensors, hardware for computation and communication, and a power supply (Fig. 1). Motes are assumed to be autonomous, programmable, and able to participate in multihop mesh communication. The genesis of Smart Dust was a workshop at RAND in 1992 in which a group of academics, military personnel, and futurists were chartered to explore how technology revolutions would change the battlefield of 2025 [2]. By this time it was clear that MEMS technology was going to revolutionize low-cost, low-power sensing. Moore’s law was accurately predicting CMOS digital circuit performance improvements with no end in sight, and the wireless communication revolution, already firmly established in two-way pagers, was beginning to make its way into handheld cellphones. The confluence of these three technological revolutions in sensing, computation, and wireless communication placed the major sensor mote functions on asymptotic curves down to zero size, power, and cost over time. Furthermore, the potential for cointegration of CMOS and MEMS made single-chip sensors with integrated signal conditioning possible at low cost [3]–[11]. In 1996, the term BSmart Dust[ was coined to describe the ultimate impact of scaling and process integration on the size of an autonomous wireless sensor [12]. Several DARPA-sponsored workshops in the mid-1990s fleshed out some of the implementation and application details of the 1992 vision, and key research proposals were written and funded at the University of California, Los Angeles (UCLA); the University of California, Berkeley; and the University of Michigan, Ann Arbor. It was clear to the community at that time that low-cost ubiquitous wireless sensor networks would have a revolutionary impact on military conflict. What was not as clearly anticipated was the potential impact on commercial and industrial applications. The first wireless sensor motes, called COTS (commercial-off-the-shelf) Dust, were built early in the Smart Dust project using printed circuit boards and offthe-shelf components. It was shown that these inch-scale devices could perform many of the functions predicted in the 1992 workshop, including multihop message passing and mote localization [13]. COTS dust and other macroscale motes were developed to explore sensor network software and individual mote architecture as well as deploy small scale networks [14]–[16]. Manuscript received August 24, 2005; revised February 21, 2006. The authors are with the University of California, Berkeley, CA 94720-1774 USA (e-mail: cookbw@eecs.berkeley.edu; slanzise@eecs.berkeley.edu; pister@eecs.berkeley.edu). Digital Object Identifier: 10.1109/JPROC.2006.873620 0018-9219/$20.00 2006 IEEE Vol. 94, No. 6, June 2006 | Proceedings of the IEEE 1177

While great strides were made in miniaturization and power reduction of the hardware, perhaps the most important event during this early period was the observation that networks of autonomous sensor motes represented a ubiquitous, embedded computing platform [17]–[20], and they needed a new operating system to match. Proposed in the Endeavour project [21], the TinyOS operating system [22] was developed under DARPA funding and put into the public domain, along with all of the COTS Dust hardware designs, and a thriving open-source sensor networking community was born. Meanwhile, in 1999 the IEEE formed the 802 working group 15, with a charter to develop standards for wireless personal area networking (WPAN), from which the lowrate WPAN 802.15.4 standard emerged. The 802.15.4 standard was designed from the beginning to be a lowpower, low-complexity solution for sensor networking in industrial, automotive, and agricultural applications [23]. A spinoff group from the industrial consortium HomeRF, focused on home automation applications, created the Zigbee standard in 2004. Zigbee 1.0 [24] is based on the 802.15.4 standard radio [25]. With the blessings of the IEEE on a radio standard, a consortium of large companies defining applications, and the help of the venture capital community, a new industry was born.

II. DEVELOPMENTS IN SENSOR MOTE HARDWARE The Mica mote (Fig. 2), the most popular mote used in research, was developed to mimic the expected architecture of a highly integrated mote while using off-the-shelf parts mounted on a common PC board to reduce development time. This mote includes a microcontroller, RF transceiver, and the ability to interface to a variety of sensors. The mote is powered by a pair of AA batteries, and these take up the majority of the unit’s volume [14]. Similar inchscale motes utilizing primarily off-the-shelf components are now commercially available from numerous sources [26]–[30]. Development of highly integrated sensor mote components started in the mid-1990s and resulted in multichip systems that could be assembled to create a mote. At UCLA, MEMS devices were combined with commercial CMOS chips that provided sensor control and readout as well as communication [31]. At the University of Michigan, Ann Arbor, a 10 000-mm3 device containing sensors, computation, and RF communication using multiple chips in a single package was developed and demonstrated [32]. Other wireless sensor multichip units or components have been demonstrated for a variety of industrial, commercial, and defense applications [33]–[42]. Fig. 1. Basic block diagram of a wireless sensor node. A complete node will consist of many blocks, most of which can be integrated onto a single standard CMOS die (blocks inside gray box). Energy storage (batteries, large capacitors, or inductors), energy scavenging, and some sensors will likely be off-chip components. The primary integrated blocks include a sensor interface, memory, computation, power management, and an RF transceiver.

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To minimize energy, passive optical communication was explored for early Smart Dust motes. The smallest optical mote to date (Fig. 3.) displaced only 4 mm3 and contained an 8-bit ADC, an optical receiver, a corner cube reflector passive optical transmitter, a light sensor, an accelerometer, a multivoltage solar cell power source, and limited computation [43]. A newer generation sensor mote, called the Spec mote, contained a microprocessor, SRAM, an RF transmitter, and an 8-bit ADC integrated onto a single CMOS die [41]. More recently, highly integrated chips with a complete RF transceiver, microprocessor, ADC, and sensor interface have been reported [44], and even commercialized [45]. Even these highly integrated chips still require an off-chip battery, some passive components, a crystal timing element, and an RF antenna, resulting in a complete package at the centimeter to inch scale.

III. WIRELESS SENSOR NETWORK APPLICATIONS Today’s sensor networks rely on a wired infrastructure to provide power and transfer data. The high cost of running wire for power and communication often dramatically exceeds the cost of the sensors themselves, slowing the adoption of sensor networks for all but the most critical applications. By drastically reducing installation costs, reliable low-cost wireless mesh networking places sensor networks on the same technology curves as the rest of the IT revolution. Wireless connectivity for sensors has been an attractive option for years, but, due to problems with reliability, adoption has been limited to applications where occasional loss of connectivity and data is acceptable. The current revolution in wireless sensing is being driven by the dramatic improvement in reliability and lifetime possible with wireless mesh networking. This is an echo of the Internet revolution, where point-to-point wired communications were replaced by multihop wired communication. The insensitivity of the Internet mesh to the loss of a path or a node is a key part of what makes the Internet reliable. The same concept applied to wireless sensor networks improves reliability. In commercial and consumer applications, motes can be used to eliminate the wiring cost for light switches, thermostats, and fire alarms. Fig. 4 illustrates the wireless routing mesh blueprint from an actual sensor network deployment. In this application, motes were installed throughout a health clinic in just 2 h to implement a low-cost air temperature and energy consumption monitoring system with a simple Web browser based control interface [46]. In applications such as inventory monitoring, motes will not be fixed in space. A primary concern of the network will be determining the location of motes on boxes or pallets on demand and this requires location discovery capability to be built into the network [47]. In some entertainment applications inertial sensing motes may be worn by humans to detect and interpret movements as communication gestures or control signals [48]–[52]. Similarly, wearable motes have been used to interpret human motion as musical gestures, allowing users to create music interactively in real time [53]. In these systems the latency requirements are more stringent than in typical monitoring scenarios and, since humans will be wearing the sensor mote, a small form factor is important. Defense applications drove much of the initial research in sensor networks. The Igloo White system was a wired sensor network employed from 1966 to 1972 along the Ho Chi Minh trail during the Vietnam War. In a more modern military application, wireless sensors were distributed throughout a mock urban battlefield to pinpoint a sniper’s location by acoustically detecting the arrival time of the muzzle blast at several different points in the field [54]. Sensor networks have also been proposed for position tracking and identification of people and fast-moving vehicles in both civilian and military scenarios [55].

IV. APPLICATION REQUIREMENTS AND HARDWARE IMPLICATIONS Applications for wireless sensor networks can be broken down into two categories: wire replacement and wirelessly enabled. In the former case, the cost of hardware for a wireless solution is generally dramatically lower than the comparable cost of running wiring. Once secure, reliable, low-power solutions are demonstrated in this domain, adoption is limited by caution, rather than cost. Wirelessly Fig. 2. The Mica mote combines sensing, power, computation, and communication into one package using off-the-shelf components.

Cook et al.: SoC Issues for RF Smart Dust Vol. 94, No. 6, June 2006 | Proceedings of the IEEE 1179

enabled applications, on the other hand, may require novel technologies such as dynamic mote localization.

A. Reliable Data Delivery Reliability in a multihop RF mesh sensor network can be defined in terms of end-to-end delivery of timestamped sensor data with a specified worst case latency. Time stamping requires some form of network synchronization, but the primary hardware impact of the reliability requirement is on the choice of radio and the use of spectrum. The majority of motes will operate in regulated but unlicensed bands, such as 902–928 MHz in North America, and 2.4–2.485 GHz throughout most of the world. Because these bands are open to transmitters putting out as much as 1 W, and motes are likely to have an output on the order of 1 mW to extend battery life, it is critical that motes be able to avoid high-power interferers to maintain adequate reliability. For example, even the spreading gain of the direct sequence spread spectrum 802.15.4 radio will not prevent an 802.11 transmitter from jamming several channels over distances of tens of meters [56]. Multipath propagation effects indoors cause similar problems for reliability, with time-varying Fig. 3. Conceptual drawing and SEM of the optical Smart Dust node presented in [43]. This multichip node displaced only 4 mm3 and featured a solar cell power source, temperature, light and acceleration sensors, an 8-bit ADC, and bidirectional optical communication.

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narrowband fading of many tens of dB commonly observed [57]. High-powered interferers and unpredictable fading preclude the use of fixed-frequency radios in highreliability applications. Reliable solutions will have the ability to avoid or work around those parts of the spectrum which are jammed or deeply faded. For relatively narrowband radios like 802.15.4, this implies some form of channel hopping at the medium access layer in addition to the direct sequence spreading defined in the physical layer of the radio.

B. Low-Power Consumption From a system deployment perspective, mote lifetimes measured in years are required for most applications in building and industrial automation. Operation from batteries and/or scavenged power is required. To avoid high battery replacement costs, this dictates a battery lifetime of between one and ten years. An AA-sized battery contains roughly 250 A-years of charge or about 12 000 J. For some lithium chemistries, the internal leakage is low enough that supplying this charge as a current of 25 A for a decade is possible while common alkaline chemistries have shorter lifetimes. The average power consumption of an inch-scale mote, then, must be in the range of tens to hundreds of microwatts or just a few joules per day. Achieving a total current consumption of tens of microamps requires deep duty cycling, on the order of 1% or less with off-the-shelf hardware [58]–[60]. Deep duty cycling implies that the hardware should be able to quickly transition between the powered state and the unpowered (and low leakage) state. At very low duty cycles, leakage power in the digital circuits, predominantly the SRAM, can dominate the system energy budget. Though the power required for active digital circuits is scaling down with minimum feature size of standard CMOS, leakage power is growing. Leakage power sets a lower bound on average power consumption of sensor motes and is a major obstacle to the scaling of digital circuits. In 130-nm bulk CMOS, for example, leakage is on the order of 1 W per kilobyte with a standard 6T SRAM [61]. Silicon-on-insulator (SOI) is a CMOS device technology offering substantial leakage reduction that has yet to be adopted into mainstream commercial use [62]. In addition to leakage issues, multihop mesh networking with radio communication in a deeply duty cycled environment presents major challenges to algorithm and software developers. Turning the radio off 99% of the time is easy, but knowing exactly when to turn it on again is not. Hardware support for some combination of mote-to-mote time synchronization, fast radio polling, or low-power detection of RF energy is desirable. Custom-designed circuits leveraging the relaxed performance specifications unique to sensor network Fig. 4. Deployment of a wireless sensor network in a health clinic. The network monitors air temperature and energy consumption and has a convenient central control interface [46].

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applications have been developed to drastically extend sensor mote lifetimes and/or reduce cost and size by minimizing energy consumption [63]–[66]. Fig. 5 provides a comparison of the energy consumption per operation of published custom ICs and off-the-shelf parts. In both commercial and custom solutions, the energetic cost of RF communication dwarfs that of other sensor node operations, making RF a bottleneck for size, cost, and lifetime improvements. In Section VI, the energy requirements of RF communication are explored and a systemlevel optimization of energy per transferred bit of a generic transceiver is performed. Unfortunately, the custom ICs presented in Fig. 5 operate optimally at different supply voltages and were not developed in the same CMOS process. Integration of these devices would require redesign in one process and efficient dc level conversion from a battery [67]. Ideally, the hardware would operate efficiently with the lithium cell potential and deep duty cycling. Since lithium chemistries generally provide over 3-V cell potential, this presents a challenge for integration in deep submicrometer CMOS, where normal supply voltages are half of the lithium potential or less. The computational requirements of a mote are generally consistent with MHz rather than GHz operation, allowing digital circuits to run as low as 0.5 V or less. Efficient dc to dc conversion from a constant 3 V supply to a duty cycled 0.5–1.8 V output will allow future systems-on-chip to achieve battery-referenced energy efficiencies similar to those shown in Fig. 5.

C. Security Security in sensor networks shares many of the same problems as IT security in general, with the beneficial exception that fewer humans are involved. As sensor networks come to be used in commercial, industrial, and defense applications, their security requirements will likely be just as stringent as those required of the information systems they feed [68]–[71]. Security requirements include access control, data encryption, message authentication, key exchange, and certification of trust. Link-level encryption and message authentication can be performed in software, but these low-level, time critical, and computationally intensive operations are a natural target for silicon support. The hardware for the Advanced Encryption Standard (AES) [72] is already incorporated in chips which support the 802.15.4 standard [60], [73]. For key exchange and certification, software implementations of the public key algorithms RSA and ECC have been demonstrated on 8- and 16-bit processors common in sensor network applications [74], [75]. Execution times are on the order of seconds to tens of seconds, and the memory requirements are substantial for a mote. The addition of integer multiplication units with large operand size will speed execution and reduce memory requirements roughly as the square of the operand size.

D. Location Discovery As the cost of motes falls and the number of wireless sensors increases, the cost of locating installed sensors will drive the development of automatic location discovery. This capability is critical for asset tracking applications and for many of the Bsprinkle deployment[ military and environmental monitoring applications envisioned for the technology. Furthermore, many applications require mobile motes with the ability to dynamically update position information [76]. Asset management and other tracking applications may require an accuracy of 1 m to find a person, laptop, or record file in an office building or hospital, several meters to find a crate in a warehouse, or many tens of meters to find a cargo container in a shipping yard. Acoustic localization systems with good performance have been implemented [77], but the physics of acoustic Fig. 5. Energetic costs of common sensor node operations based on commercially available hardware and lowest energy published solutions.

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propagation constrain the domain of application of these systems. GPS may be very useful for localizing parts of a sensor network, but in general motes will not have the satellite visibility necessary for these systems, even if the power requirements could be met. One solution is a pairwise range sensor coupled with either centralized or distributed computation of position based on the sparse pairwise data [78], [79]. Measurement of received RF signal strength has been proposed as a surrogate for a range sensor, but multipath fading makes this technique unsuitable for most applications [76], [80]. Localization based on RF time-of-flight (TOF) between motes is currently being investigated as a more accurate solution [81]. Multipath propagation of radio waves and clock drift between motes are the primary contributors to error in RF TOF systems, and these problems must be addressed and mitigated in a reasonable system.

V. SYSTEM INTEGRATION: FEASIBILITY OF A SINGLE-CHIP SENSOR MOTE The mock-up device at the bottom of Fig. 13 below represents a hypothetical 2-mm3 mote-on-a-chip combining cutting-edge process integration and circuit techniques. In reality, the most integrated mote-on-a-chip systems today still require several off-chip components. Given recent advances in process integration, this section explores the possibility of integrating each system block on-chip to create a cubic millimeter scale complete sensor mote.

A. Cointegration of Digital, Analog, and RF Any sensitive analog circuits must be isolated from the noise-generating digital devices of the DSP and microprocessor. Integration of both devices is commonplace today as process features and design techniques have been developed to isolate digital circuits from analog [82], [83]. Many circuits typically found in an RF transceiver require elements not needed for digital or low-frequency analog operation, such as inductors and high-density capacitors with low series resistance. Thus, RF circuits have historically required several off-chip components. Only recently have IC manufacturers added process features targeted at enabling integration of RF circuits. Currently, several manufacturers offer high density capacitors and thick top metal layers for inductors. Due to these process advancements, modern RF transceivers are approaching complete integration [84]. Even with integrated RF passive components, there are still a few elements impeding complete integration of RF transceivers, namely the antenna and timing reference. The antenna is difficult to integrate because its optimal dimensions are on the same order as the wavelength of the RF signal, making antennas in the low-GHz range ill-suited to integration. The optimal dimensions can be scaled down by increasing frequency and making the antenna resonate, leading many to investigate integrated resonant antennas at and above 10 GHz [85]–[87]. Even at appropriately high frequencies, integrated antennas have thus far only demonstrated low efficiencies. Furthermore, propagation losses are generally worse at higher frequency. As a result, an integrated antenna will incur a substantial power penalty with current technology. If a modest size increase and some assembly are acceptable, commercially available miniaturized antennas may provide the best combination of cost-effectiveness, size, and efficiency. Efficient dielectric chip antennas displacing only about 10 mm3 are commercially available for use at low-GHz frequencies from a variety of sources [88], [89]. However, as designed, these chip antennas require sizable ground planes for good performance. The timing reference is another element of RF transceivers not amenable to integration. RF transceivers typically use a resonant quartz crystal to synthesize high frequency signals needed for transmission and reception. The geometry of crystal references is precisely controlled to create a mechanical resonance that is stable across a wide temperature band. There are no conventional circuit elements that can offer precision comparable to a crystal. However, MEMS resonators are currently being explored in industry and academia as a quartz crystal replacement technology because of their potential for integration and cost reduction [90]–[93]. Currently, the temperature stability of MEMS resonators is not as good as quartz crystals, but temperature compensation may be employed to mitigate this problem [94]. As this technology matures, MEMS components may supplant not only the crystal timing element, but filters, mixers, and RF oscillators as well [95].

B. Sensors For some applications, the sensors available in a standard integrated circuit process may be sufficient. Temperature, magnetic field, and capacitive fingerprint sensors have all been demonstrated in standard CMOS as well as megapixel cameras with on-chip image processing [96]–[100]. Integrated sensing of colored light can also be done in CMOS using metal grating patterns or variable depth PN junctions as a color filter [98], [101]. Imaging arrays are increasingly finding applications in noncamera applications, such as motion-flow sensing in computer mice. Imaging of legacy dials, knobs, and lights in industrial environments combined with local signal processing at the sensor to transmit only the dial position is a potentially low-power, low data rate application. There are a host of miniaturized sensors possible with MEMS technology: linear and angular rate acceleration, pressure, chemical, fluid flow, audio microphones, and more [3], [4], [102]–[105]. While all of these sensors are also available off-the-shelf, custom designed MEMS sensors have the distinct advantages of low cost and size as well as the potential for integration with circuits.

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Many methods of integrating MEMS devices with circuits have been demonstrated. One popular method is to etch away materials from commercially manufactured integrated circuit wafers to create mechanically free structures. The features of the resulting structures are defined using existing layers in the CMOS to selectively block etching. In [3], [4], [8], and [11], an electrochemical etching technique was applied to standard CMOS wafers after fabrication to create cantilevered beams and membranes for chemical, infrared, pressure, and other types of sensors. Dry etching techniques were applied to CMOS wafers in [7] and [106], to create inertial sensors and electrostatic actuators. An advantage of both of these integration techniques is low cost because no additional deposition or lithography is necessary after the circuits are fabricated (see Fig. 6). However, since the MEMS structures are defined by a stack of dielectrics and metals designed for CMOS, they may have undesirable mechanical properties. The performance of resonant MEMS devices used for both sensing and RF applications is particularly sensitive to the mechanical properties of the constituent materials. Thus, many have investigated other integration methods that permit the use of mechanically advantageous materials. Adding thin films of polycrystalline materials to fabricated CMOS wafers, or surface-micromachining, is a powerful technique that combines the advantages of integration with CMOS and high performance resonant MEMS. Integrated high-Q MEMS resonators and resonant sensors made from both polycrystalline Silicon (poly-Si) and silicon–germanium (poly-SiGe) films have been demonstrated with surface-micromachining techniques [5], [9], [10]. Unfortunately, the elevated processing temperatures required for poly-Si (well above 400 C) are too high for the aluminum metallization typical of standard CMOS. Thus, integrated poly-Si MEMS must either be machined into the wafers before metallization steps [9], [10] or added to fabricated CMOS without metallization [5]. However, the reduced processing temperatures of poly-SiGe are much more compatible with metallization, making postprocessed poly-SiGe a strong candidate for the future of CMOS-MEMS integration (see Fig. 6) [6], [104].

C. Scavenging and Storing Energy Both electrostatic MEMS devices and PZT transducers have been used to harvest energy from ambient mechanical vibrations [107]–[110]. It should be possible to Fig. 6. Demonstration of MEMS-CMOS integration by four different techniques. Top left: electrochemical etching [8] (SEM courtesy of G.T.A. Kovacs), Top right: deep reactive ion etch(DRIE) of single-crystal silicon bonded to CMOS [11] (SEM courtesy of G.T.A. Kovacs), bottom left: DRIE of prefabricated CMOS with metal-dielectric structural layers [7] (SEM courtesy R.T. Howe), bottom right: postprocessed SiGe on CMOS [6] (SEM courtesy G. Fedder).

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integrate these devices, since vibration harvesting may be performed with simple electrostatic MEMS. The achievable power density with this method is strongly dependent on the environment and the design of the transducer. However, theory predicts a power density of 1.16 W/mm3 is available from a device mounted on the casing of a constantly operating microwave oven [110]. The most abundant and practical form of ambient power comes from the sun. In full sunlight, the available solar power per unit area is roughly 1 mW/mm2 in the continental United States [111]. Simple silicon-based photovoltaic cells can convert this to electrical power with up to 25% efficiency [112]. The processing steps necessary to create silicon solar cells are quite compatible with standard IC manufacturing. In fact, the PN junctions inherent in the silicon of any integrated circuit are inadvertent solar cells. However, with standard CMOS, it is not straightforward to utilize these junctions as solar cells and simultaneously operate transistors on the same chip due to isolation issues. Integration of multijunction solar cells and CMOS circuitry has been demonstrated using silicon-on-insulator wafers with trench isolation [113]. Miniature, but not integrated, solar cells are currently available off-the-shelf from a variety of manufacturers. In particular, silicon-based, flexible, thin-film solar cells mounted on polymer substrates are now commercially available in custom sizes on the order of 1 mm2 and up [114]. To sustain reliable operation in the presence of fluctuating ambient solar or mechanical energy, a sensor mote must be able to store harvested energy. A promising technology for integrated energy storage is thin-film batteries. Work at Oak Ridge National Laboratory on lithium-based thin-film batteries [115] has led to commercial cells on the millimeter scale with high capacity and long cycle lives [116]–[120]. Packaging adds volume without increasing capacity, resulting in lower energy/volume ratios, but [115] reported 0.25 mA hr/cm2 at 4 V (or 36 mJ/mm2) in batteries as small as 5 mm2 and only 15 m thick without packaging. Battery discharge rates as high as 40 mW/cm2 are possible [115], and these cells can be laminated to a CMOS wafer, eliminating the need for packaging [117]. Cells as small as 50 m 50 m have been demonstrated using standard lithographic techniques [121]. Other recent work in thin-film batteries has produced promising results with lower cell potentials, but the cell capacity and robustness is far behind solid-state lithium-based batteries [122], [123].

VI. ENERGY REQUIREMENTS OF WIRELESS COMMUNICATION Based on a comparison of published solutions for RF transceivers and other sensor mote functions, the wireless communication circuits dominate the system energy budget. This section explores the energy requirements of wireless communication and derives approximate energy targets. As a first step, consider transmitting a single bit from one sensor mote to another over a distance r, using a carrier frequency f, and bitrate b. To determine the minimum required transmission power ðPTX;MINÞ, one must first determine how the signal power diminishes with distance, and then determine the minimum detectable signal power in the receiver ðPMDSÞ. If a maximum communication range ðrÞ is assumed, then PTX;MIN must be larger than PMDS by a factor equal to the transmission loss ðLPATHÞ due to propagation.

A. Transmission Loss Approximations: LPATH Electromagnetic theory states that the strength of a transmitted signal is attenuated with increasing distance according to the Friis equation [124] LPATH ¼ 4r 2 : (1) LPATH is the attenuation due to propagation and is the wavelength at the frequency of interest ( ¼ 30 cm at f ¼ 1 GHz). The Friis equation applies to free-space, line of sight propagation and, as such, underestimates path loss for nonideal conditions. In cluttered environments, path loss is much more complex. Several sources have utilized a modification to the Friis equation that roughly approximates propagation losses in less ideal environments, such as indoors [80] LPATH ¼ 4r0 2 r r0 n : (2) In this model, ro is a reference distance (ro ¼ 1 m is often used) beyond which the inverse square characteristic of the Friis equation no longer governs propagation losses because of obstacles and multipath interference. The exponent n characterizes the attenuation beyond ro and has been measured for various propagation conditions. For short-range indoor propagation in the low GHz range, n ¼ 4 is a common choice for the exponent [80], [125].

B. Minimum Detectable Signal Power: PMDS In any real receiver, there is a finite thermal noise power ðPNÞ inherent in the system that is proportional to both input bandwidth, BW, and the product kT; where T is temperature in Kelvin and k is Boltzmann’s constant PN ¼ kT BW: (3)

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The minimum detectable signal power in a receiver ðPMDSÞ is always greater than PN. The product of two terms, noise factor ðNFÞ and signal-to-noise ratio ðSNRMINÞ, quantifies the ratio by which PMDS must exceed PN for successful transmission. The noise performance of RF receivers is characterized by NF, defined as the ratio of the total equivalent noise power to the fundamental lower noise power limit PN. In the best case, NF equals 1, but it is often in the range of 1.5–10 for real receivers. Intuitively, higher NF implies that the receiver’s internal noise generators dominate over the noise incident on the antenna. The second term SNRMIN, describes the minimum required ratio of signal power to noise power that must be maintained to properly detect signals with a certain probability. For example, to average less than one error for every 1000 bits (or BER ¼ 103), a theoretical minimum SNRMIN of 12 dB is required when noncoherent FSK is the modulation technique and no coding is done [126]. Under these assumptions, the minimum detectable signal power in the receiver is given by product PMDS ¼ PN ðNF SNRMINÞ ¼ kT BW NF SNRMIN: (4)

C. Minimum Transmlission Energy per Bit: EBIT;TX Link margin ðLMÞ quantifies the maximum path loss between transmitter and receiver that can be tolerated while maintaining a reliable link. LM is given by the ratio of POUT to PMDS. At the maximum communication range ðrMAXÞ, LM is equal to LPATH. Therefore, given rMAX, the lower bound on transmitted power ðPTX;MINÞ is simply the product of LPATH and PMDS. POUT;MIN ¼ LPATH PMDS ¼ 4 r0 2 rMAX r0 n kT BW NF SNR: (5) To convert POUT;MIN to energy per bit ðEBIT;TXÞ, we must assume a relationship between the bitrate and the receiver input bandwidth BW. Bitrate is generally proportional to input bandwidth and, depending on the modulation technique, may be higher or lower than BW. For simplicity, we assume the bitrate is equal to BW. Then, EBIT;TX is given by EBIT;TX ¼ POUT;MIN bitrate 4r0 2 rMAX r0 n kT NF SNRMIN: Let bitrate ¼ BW: (6) To calculate the minimum EBIT;TX, assume the base station is an ideal, noncoherent FSK receiver (i.e., let NF¼1 and SNRMIN ¼12 dB) located rMAX meters away and apply (6). Assuming n ¼ 4, ro ¼ 1 m, rMAX ¼ 20 m and a 1-GHz carrier signal, the minimum energy per transmitted bit is only 20 pJVa factor of at least 102 lower than any of the reported values from Section IV. In this scenario, if a bitrate of 1 Mb/s is used, only 20 W must be transmitted to maintain a 20-m link. On the other hand, if a 2.4-GHz carrier is chosen, the minimum energy Fig. 7. Simplified block diagram of a low-IF or direct conversion RF transceiver.

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per bit increases to 114 pJ, because path loss is worse at higher frequencies. This calculation represents the minimum transmitted energy to reach a perfect receiver (i.e., NF ¼ 1) 20 m away. The total consumed energy by the transmitter must be substantially higher due to overhead circuit power ðPOH;TXÞ and nonideal efficiency in the output amplifier ðePAÞ.

D. Design Considerations and Practical Targets for EBIT When calculating network energy cost per bit, the power consumption of both the transmitting and receiving motes should be included. Second, the models for transmitter and receiver should take overhead power and nonideal SNR, NF, and PA efficiency ðePAÞ into account. A block diagram of a conventional direct-conversion or lowIF transceiver, labeled with sources of overhead power, is shown in Fig. 7. The outlined portions of Fig. 7 represent sources of power overhead. Though these blocks are needed for functionality, they constitute overhead in the sense that increasing power spent in them does not directly increase link margin. In both transmitter and receiver, a large portion of the overhead power is dedicated to generating a stable RF signal with a voltage controlled oscillator (VCO). Other significant sources of overhead are RF mixers for modulation and channel selection, ADCs, DACs, and lowfrequency filters. The power overhead of the VCO and RF mixers is relatively independent of BW. However, the overhead power in the DAC, ADC, and low-frequency filters for channel selection and baseband processing will depend on BW. Radios designed specifically for sensor networks in [63] and [127]–[130] reported numbers for power overhead between 0.17 and 0.9 mW in receive mode, 0.3–7 mW in transmit mode for bitrates of 300 kb/s and below. In contrast, increased power in the PA and LNA does directly increase link margin. In general, increased power in the LNA makes the receiver more sensitive by decreasing NF, but the proportional noise benefit steadily diminishes at high power levels as NF asymptotically approaches its minimum value of 1. On the other hand, the output of a PA can be roughly proportional to power consumed over a wide range. Efficient PA design over a broad range of power outputs is discussed in [131]. Power output of a PA can then be simply modeled by the product of efficiency ðePAÞ and power consumed ðPPAÞ. PA efficiencies ðePAÞ of 40% or higher have been reported for various PAs with output power from 200 W to 10 mW and beyond [127], [129], [132].

E. Optimal Bandwidth to Minimize EBIT Fig. 8 shows a first-order graphical representation of the power-performance tradeoffs in a simple RF Fig. 8. Graphical representation of first order model of power-performance tradeoffs in an RF transceiver. Labeled numeric values are based on the transceiver in [77].

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transceiver. The figure is labeled with reported values of POH;TX, POH;RX, PMDS and ePA from [127]. The simplified model is useful for demonstrating tradeoffs and deriving approximate energy consumption targets. Measured data reported in [63] is shown in Fig. 9 for comparison. The equations describing this model are given below. The term is dependent on antenna impedance, supply voltage, and other circuit parameters (see [131]), but is equal to 2 mW for the transceiver in [127] POH ¼ POH;RF þ PBB 1 þ BW BW0 (7) PMDS ¼ kT BW SNRMIN 1 þ PLNA (8) POUT ¼ ePA PPA: (9) The first question we wish to address is: Given a fixed power budget for a link, how should power be distributed between PA and LNA to maximize link margin ðLMÞ? Dividing (9) by (8), we get an equation for LM in terms of power consumption in PA and LNA. The goal is to maximize LM when the sum PPA þ PLNA is held constant, and the resulting equation, optimally relating LNA and PA power consumption, is shown below max PPAþPLNA¼C f g LM ) dLM dðPLNAÞ ¼ 0 ) PPA ¼ P2 LNA þ PLNA: (10) This ratio is independent of the path loss exponent assumed in (2). It is important to note that we have implicitly assumed a time synchronized network, where Fig. 9. Measured transceiver performance data reported in [63]. This 2.4-GHz radio operates from a 400-mV supply and achieves 4-nJ/bit communication with 92-dB link margin. PA efficiency is 44% and the power overhead is estimated as POH;TX ¼ 400 uW and POH;RX ¼ 170 uW.

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receiver and transmitter duty cycles are approximately equal. By setting LM ¼ LPATH from (2), we can use (8) and (9) to relate transceiver power consumption to range ðrMAXÞ and bitrate (again, assume bitrate ¼ BW) rMAX ¼r0 4r0 2 n ePA PPA kT BW SNRMIN PLNA PLNAþ 1 n : (11) Now, using (10) to relate PPA and PLNA PLNA;OPT ¼ rMAX r0 n 2 4r0 ePA kT BW SNRMIN 1 2 : (12) Fig. 10. Energy per bit and transceiver power distribution versus bandwidth for fixed link margin of 88 dB ( ( 3)). e.g., r 25 m by

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To incorporate the effect of transceiver startup time on the overall EBIT versus BW tradeoff, some knowledge of average number of data bits per transmission ðNAVGÞ and transceiver initialization, synchronization, and packet overhead time ðtINITÞ is needed. For the purpose of illustration, we assume NAVG ¼ 1000 bits and tINIT ¼ 1 ms. Assuming the transceiver is consuming full power during synchronization, the energy cost per bit is then the product of total link power and tINIT divided by NAVG EBIT;INIT ¼ ðPOH þ PPA þ PLNAÞ tINIT NAVG : (14) The total energy per bit, including initialization and transmission, is the sum of (13) and (14). EBIT is minimized Fig. 12. Top: optimum ratio of PA to LNA power. Bottom: energy per bit per meter (EBIT-MTR) versus the sum of PA þ LNA for 3 values of the path-loss exponent(n). Optimum link margin and range are labeled for each value of n.

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when the amount of energy spent during synchronization and data transmission are equal, or equivalently (see Fig. 10) BWOPT ¼ NAVG TINIT : (15)

F. Optimal Link Margin and Range to Minimize EBITMTR Suppose we wish to send a set of data over a long distance through a dense network with many available paths (Fig. 11, bottom). From a global network energy perspective, should we send the data the entire distance in one hop, in several tiny hops to nearest neighbor motes, or is there an ideal link range somewhere in between? In dealing with this question, energy per bit per meter ðEBIT MTRÞ is a more appropriate metric than EBIT. If path loss characteristics are known, we can find an optimum link range that will minimize the global network energy cost for data transport by minimizing EBIT MTR. Since (13) relates EBIT to both BW and r, EBIT MTR can be obtained by simply dividing EBIT by r. EBIT MTR is plotted versus power with BW fixed at 1 MHz for three values of the path-loss exponent at the bottom of Fig. 12. This plot shows that there exists an optimum energy range and link margin for transporting data through a network that depends on path-loss conditions and transceiver characteristics. The optimum link margin ðLM;OPTÞ varies by only 11 dB for values of n from two to four and has the lowest value when the path-loss exponent is highest, implying shorter hops are preferred when path-loss is worst. A more circuit focused link optimization is carried out in [131]. All quantitative information in this example has been based upon an extrapolation of transceiver performance data reported in [127]. The actual transceiver was designed for a 100 Kb/s bitrate and about 20 m of range, with a resulting EBIT;MIN of about 25 nJ/bit.

VII. DISCUSSION It is clear that a system-on-chip wireless sensor node with an active power dissipation of less than 1 mW is not only possible, but likely to be commercialized. The performance possible in such a mote will be impressive, including secure wireless communication at hundreds of kilobits per second over distances of tens of meters, multihop mesh networking, onboard sensors, 10- to 16-bit ADCs, and a sensor datapath. Today’s commercially available software runs all motes in a mesh network at less than 1% radio duty cycle [26]. This implies average mote power consumption of between 1 and 10 W. At these power levels, mote lifetimes above a decade will be possible with coin cell, or even button-cell batteries. Near-term IC process scaling will reduce the area required for memory and digital circuits to below a square millimeter, but the analog and RF portions will not scale as readily. Radio transceivers are unlikely to shrink much in finer line width processes, as their area is determined more by the physics of inductors than the transistors that drive them. Unless integrated resonant LC tanks are abandoned, low-GHz radios are stuck around a square millimeter. Process scaling driven by purely highspeed digital constraints is unlikely to provide the low leakage necessary for submicrowatt operation, but other Fig. 13. A complete sensor node may be implemented with varying levels of integration. While the cost, size, and power consumption of off-the-shelf sensor nodes is far from optimal, a single-chip system may not be the most advantageous either. The most economical solution is likely to be a hybrid of integrated and assembled parts. Cook et al.: SoC Issues for RF Smart Dust 1192 Proceedings of the IEEE | Vol. 94, No. 6, June 2006

applications will drive low-leakage options in fine-line width processes, and clever circuit design may solve the leakage problem even in standard processes. MEMS technology is likely to play a role in the integration of a broader selection of sensors on chip. In addition, RF filters and frequency references for both realtime clocks and RF local oscillators are possible. Similarly, nanotechnology is likely to be added first in the area of sensors. Improvements in the stability of low-power realtime clocks, based on MEMS, nano, or any other technology, would have an immediate impact on moteto-mote time synchronization and therefore power consumption. The integration of MEMS or nano could in principle reduce the size of radios well below a square millimeter, but these radios will face the same challenging RF environment as the radios that they replace, so frequency agile architectures with robustness to strong interference and deep fading will be required. While in principle it is possible to integrate a battery, antenna, and timing reference into a single-chip mote with no external components, this is unlikely to be the most economical approach. Integration of all the components of a mote onto a single chip will involve making substantial sacrifices in performance. The efficiency of a millimeter-scale chip-based antenna will be lower than that of a well designed antenna external to the chip. Power scavenging and storage in a future integrated process will not match what is possible with optimized off-chip components. On the other hand, on-chip timekeeping and frequency references using MEMS or nano may ultimately rival or even exceed the performance of off-chip crystal references. Fig. 13 illustrates some possible incarnations of a wireless sensor mote, underscoring size, power, and performance tradeoffs of integration versus assembly. For all of the performance and cost limitations of a true system-on-chip mote with no external components, surely at some point they will be produced, if only for academic research. When that is the case, then wafers full of completely functional motes will be formed in the final metal etch of a CMOS process, take their first photovoltaic breaths of life from the plasma’s glow, and start chatting with each other while waiting for wafer passivation and dicing.

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Cook et al.: SoC Issues for RF Smart Dust Vol. 94, No. 6, June 2006 | Proceedings of the IEEE 1195

ABOUT THE AUTHORS Ben W. Cook (Student Member, IEEE) received the B.E. degree from Vanderbilt University, Nashville, TN, in 2001. He is currently working toward the Ph.D. degree at the University of California, Berkeley. Since the summer of 2003, he has worked as a Design Engineer and Consultant for Dust Networks, Hayward, CA, where he has worked on ultralow-power transceivers for the 900-MHz and 2.4-GHz ISM bands. His research has focused on low-power, highly integrated hardware for wireless sensor networks, with a particular emphasis on RF transceivers. Steven Lanzisera (Student Member, IEEE) received the B.S.E.E. degree from the University of Michigan, Ann Arbor, in 2002. He is currently working toward the Ph.D. degree at the University of California, Berkeley. He was an engineer with the Space Physics Research Laboratory at the University of Michigan from 1999 to 2002, where he worked on satellite integration and testing. He has held internships with Guidant Corporation and TRW Space Systems, respectively. His research has focused on low-power mixed signal IC design and RF time of flight ranging technologies. Kristofer S. J. Pister received the B.A. degree in applied physics from the University of California, San Diego, in 1986 and the M.S. and Ph.D. degrees in electrical engineering from the University of California, Berkeley, in 1989 and 1992. From 1992 to 1997 he was an Assistant Professor of Electrical Engineering at the University of California, Los Angeles, where he helped developed the graduate microelectromechanical systems (MEMS) curriculum, and coined the term BSmart Dust.[ Since 1996, he has been a Professor of Electrical Engineering and Computer Sciences at the University of California, Berkeley. In 2003 and 2004, he was on leave from the University of California, Berkeley, as CEO and then CTO of Dust Networks, Hayward, CA, a company he founded to commercialize wireless sensor networks. He has participated in many government science and technology programs, including the DARPA ISAT and Defense Science Study Groups, and he is currently a member of the Jasons. His research interests include MEMS, micro robotics, and low-power circuits.